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Power Systems Computation Conference 2024

Proceedings of the 23rd Power Systems Computation Conference - PSCC 2024 »

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Implementation and Validation of a Dual P- and M- Class Compliant PMU Prototype Based on the Delayed In-Quadrature Interpolated DFT

In this paper, the design and experimental validation of a prototype phasor measurement unit (PMU) that simultaneously meets the P and M class requirements of the IEC/IEEE Std 60255-118-1-2018 are presented. The device is based on a synchrophasor estimation (SE) algorithm, previously formulated by the authors, which exploits the generation and use of a delayed in-quadrature complex signal to mitigate the self-interference of the fundamental tone. The method is deployed to a NI CompactRIO-9039 platform, requiring a total use of 19.2% flip-flops, 50.6% LUTs, 77.9% DSPs and 13.7% BRAM for a single-channel configuration and operating under a 50-fps report rate, 50 kHz sampling rate, and three nominal cycle observation windows. A PMU calibrator is used to perform a comprehensive metrological analysis of the device and verify its compliance with the standard. The results show that the prototype meets the requirements of both P and M classes with a worst-case measurement reporting latency of 36.21 ms.

César García Veloso
University of Seville
Spain

Mario Paolone
École Polytechnique Fédérale de Lausanne
Switzerland

José María Maza Ortega
University of Seville
Spain

Alexandra Cameron Karpilow
École Polytechnique Fédérale de Lausanne

 


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